1. Field
Various embodiments of the present invention relate to a buffer circuit and an operation method thereof.
2. Description of the Related Art
Recently, a technical trend of a semiconductor device is concentrated on a low power operation. Various proposals have been introduced to reduce a standby current of internal circuits of a semiconductor device to achieve low power operation. For example, a plurality of buffer circuits may be included in the semiconductor device. Moreover, reducing a current consumption of the buffer circuits may lead to a low power operation of the semiconductor device.
In general, a two-stage amplifier is used as a buffer circuit. Since the two-stage amplifier has a two-pole configuration, it is needed to secure a phase margin more than 60 degrees for frequency stability. Additionally, since a load capacitance coupled to an output terminal of the buffer circuit is relatively large, the load capacitance of the buffer circuit has an influence on the phase margin. To optimize the phase margin of the buffer circuit according to a position of a pole of an input node and a pole of an output node, an amount of sinking current of the two-stage amplifier is adjusted using a bias applied from an external device.
Furthermore, a voltage level of an external voltage such as a power supply voltage, is linearly increased from 0 V to a target voltage level. A semiconductor device activates a power-up signal and initiates an operation thereof when the external voltage reaches the target voltage level. During the power-up of the semiconductor device, a conventional buffer circuit may not uniformly maintain a charge amount corresponding to the load capacitance. Due to a coupling effect, an output voltage of the buffer circuit is increased compared to an input voltage thereof.
When a sinking current amount of the buffer circuit is reduced due to a low power operation, a discharge time for discharging an output terminal of the buffer circuit may be delayed, that is, a settling time of the buffer may be increased. The settling time represents a time in which the output voltage of the buffer circuit reaches a target voltage level.